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Chip players join to create `cool' silicon for mobiles

By Anand Parthasarathy

BANGALORE, MARCH 22. The battery going dead, just as you were about to make that important call from your mobile? The handset getting — literally — `too hot' to handle, after an hour's intensive use?

These familiar hassles of cellular phone users may soon be a thing of the past. This is the hope held out by an interesting coming-together today of five leading global players in the business of silicon chip design and production. They have announced a Silicon Design Chain Collaboration — a combo of hardware and software tweaks — that has resulted in a dramatic (40 per cent) reduction in the power consumed by a typical mobile system-on-a-chip (SOC).

For the first time, such power saving technology that reduced leakage and battery consumption, on one hand and cuts heat dissipation on the other, has been successfully validated in silicon, using the latest 90-nanometre (nm) fabrication process, explained Himanshu Singh, Executive Director (India/SAARC) of Cadence Design Systems, the world's largest electronic design automation (EDA) player.

High tech `Band of Brothers'

"There was no way any single company could have achieved this,'' Mr. Singh added, suggesting that collaboration was the key to this high tech "Band of Brothers'' effort. While Cadence contributed the necessary suite of design tools, the U.K.-based ARM and its associate company, Artisan, provided the standard memory libraries and the testing muscle; the U.S.-based Applied Materials, "chipped'' in with the 90 nm production facilities and the Taiwan based TSMC, provided the actual silicon foundry facilities.

The power-efficient design was realised on the industry-standard ARM 1136JF-S chip that fuels many mobile phones and portable wireless devices. In the process, the partners succeeded in reducing the operating voltage for many sub-circuits from one volt to 0.8 volt — which contributed its own efficiencies.

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